Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems communicate with various devices using standard network interface and standard computer bus architectures. Direct memory access (DMA) requests are used to move data to/from a host system memory. DMA modules (also referred to as channels) are typically used to move data to and from a host system memory. DMA modules provide address and control information to generate read and write accesses to host memory.
A single DMA channel typically breaks up a DMA data transfer request from a host system into smaller requests to comply with interface protocol requirements. Some of the factors affecting the break up of a DMA request include payload size requirement and address boundary alignment on a PCI-X/PCI-Express interface (or any other interface), and frame size negotiation on fibre channel interface and others.
In conventional systems, often a DMA channel generates a request with a fixed or minimum frame size. This is based on being able to transfer a packet/frame (collectively referred to as data) of a particular size. However, a DMA channel may have more data available for transfer between the time it generates the DMA request and when an arbitration module grants access. The conventional approach of generating DMA requests based on fixed size is static and undesirable because the DMA channel can only transfer data that it specifies in the DMA request regardless of whether more data is available for transfer. This shortcoming is especially undesirable in high bandwidth network operations (for example, 1 Gigabit (G) to 10 G networks) because it results in latency. Therefore, optimizing DMA request handling continues to be a challenge in the computing industry.